Complementary metal oxide semiconductor (CMOS) circuits of current semiconductor technology comprise n-type field effect transistors (nFETs), which utilize electron carriers for their operation, and p-type field effect transistors (pFETs), which utilize hole carriers for their operation. CMOS circuits are typically fabricated on semiconductor wafers having a single crystal orientation. In particular, most of today's semiconductor devices are built on Si wafers having a (100) crystal orientation.
It is known that electrons have a high mobility in Si with a (100) crystal orientation and that holes have high mobility in Si with a (110) crystal orientation. In fact, hole mobility can be about 2 to 4 times higher in a 110-oriented Si wafer than in a standard 100-oriented Si wafer. It is therefore desirable to create a semiconductor substrate that comprises both 100-oriented Si surface regions, on which nFETs can be formed, and 110-oriented Si surface regions, on which pFETs can be formed. Semiconductor substrates that contain surface Si regions of different crystal orientations are hereby referred to as multi-orientation substrates.
There is a continuing need for improved multi-orientation substrates, especially for multi-orientation substrates that have complete SOI structures. There is also a need for improved methods for fabricating high quality multi-orientation substrates at lower costs with less processing steps.